1. Field of the Invention
The present invention relates to a process for chemical mechanical polishing (which may hereinafter be referred to “CMP”) of semiconductor substrates and an aqueous dispersion for chemical mechanical polishing. More specifically, the present invention relates to a process for chemical mechanical polishing that is particularly useful for chemical mechanical polishing a wafer having a wiring pattern and an insulating layer having a low dielectric constant is formed between wiring patterns, interlayers in the case of a multi-layer wiring and the like in the process of producing a semiconductor device, and an aqueous dispersion for chemical mechanical polishing which is used in this process.
2. Description of the Related Art
A SiO2 layer formed by a vacuum process such as a CVD method is conventionally used as an insulating layer formed on a semiconductor element and the like. In recent years, more attention is being focused on achieving a lower dielectric constant of the insulating layer for the purpose of improving VLSI performance. Lower dielectric constants have been achieved by the development of insulating layer, in place of SiO2 layer with a high dielectric constant, including, silsesquioxane (dielectric constant; approximately 2.6 to 3.0), fluorine-containing SiO2 (dielectric constant; approximately 3.3 to 3.5), polyimide-based resins (dielectric constant; approximately 2.4 to 3.6, trade name; “PIQ” by Hitachi Chemical Industries Co., Ltd.; trade name; “FLARE” by Allied Signal Corp., and the like), benzocyclobutene (dielectric constant; approximately 2.7, trade name; “BCB” by Dow Chemical Corp., and the like.), hydrogen-containing SOG (dielectric constant; approximately 2.5 to 2.5) and organic SOG (dielectric constant; approximately 2.9, trade name; “HSGR7” by Hitachi Chemical Industries Co., Ltd.) and the like. Since these insulating layers have low mechanical strength and are soft and brittle as compared to SiO2 layers, however, they sometimes produce a large number of scratches having large or small shapes with a conventional CMP method.
In addition, as shown in FIG. 1, in the case a surface of a semiconductor substrate having a wiring board formed by stacking an insulating layer 2 having a low dielectric constant on a substrate 1 comprised of silicon wafer and the like, forming a trench part 5, and depositing a metal 4 as a wiring material on the whole surface of the substrate with a trench on which a barrier metal layer 3 has been formed, is polished, the following undesirable phenomenon is observed in some cases. That is, the insulating layer having a low dielectric constant as a lower layer peels from its periphery during polishing at a step where the insulating layer having a low dielectric constant is not exposed on the polishing surface, that is, at a step where only a metal layer as a wiring material is chemically mechanical polished.
In order to solve the problem as described above, a variety of methods have been proposed.
For example, a technique has been described which can suppress surface defects of a surface to be polished when a metal layer is chemically mechanical polished using a silica particle as an abrasive, (for example, in JP-A-2001-110,761). In addition, another technique has been described which can suppress surface defects of a surface to be polished by a slurry containing no solid abrasive (for example, in WO 00/13,217 pamphlet).
In these techniques, the insulating layer having a low dielectric constant as described above is not supposed as a material to be polished, however, suppression of occurrence of scratches, peeling at a periphery part and the like on the material to be polished during chemical mechanical polishing, are not studied.
On the other hand, an attempt has been made to reduce scratches generated during chemical mechanical polishing of an insulating layer having a low dielectric constant by lowering a pressing pressure of a polishing head of a chemical mechanical polishing apparatus. However, when a chemical mechanical polishing of the above-mentioned stacked material is performed by using the previously known chemical mechanical aqueous dispersion under the conditions of lowered pressing pressure of the polishing head, a sufficient removal rate is not obtained. This is particularly true at a step where the insulating layer having a low dielectric constant for which occurrence of scratches should be reduced is not exposed on the surface to be polished. That is, at a step where only a metal layer comprised of copper, tungsten, aluminum or the like as a wiring material is exposed thereon. As a result there is a problem of insufficient throughput with such a process.